In the classroom

All too often, students are taught yesterday’s technology, when they should be learning the skills that will enable them to impact the future. RTL languages simply cannot sustain the future of this industry, and teaching RTL positions students on the wrong side of the curve.

But let's put language aside. It is the concepts that students must learn, and TL-Verilog and are, without a doubt, the easiest way for them to learn.

TL-Verilog simplifies. With VHDL and Verilog, classes get bogged down by the details of the language. TL-Verilog eliminates from Verilog the need for:

  • blocking vs. non-blocking assignments

  • packed vs. unpacked datatypes

  • reg vs. wire vs. logic vs. bit

  • sensitivity lists

  • always blocks

  • generate blocks

These are a constant source of confusion for students (and professionals alike) and have nothing to do with digital logic. 


Language == concepts. By learning TL-Verilog, students learn a clear thought process for advanced logic design. The constructs of the language are the concepts to be taught:

  • combinational logic

  • sequential logic

  • pipelines

  • state

  • hierarchy

  • transactions

You will be amazed how much you can teach your students when the language is not getting in the way. In the time it took you to read this far, your students could be coding and simulating their first combinational logic in Makerchip

TL-Verilog and Makerchip are ideal for:

  • Intro to Digital Logic

  • Computer Architecture

  • FPGA Design Labs

For remote learning, our open-source 1st CLaaS cloud FPGA framework is ideal for virtual FPGA labs.

These videos exemplify just how much students can learn in a single lecture.


Steve Hoover presents ideas for professors faced with the challenge of converting to remote learning. He demonstrates the value of Makerchip for digital logic classes and the use of cloud FPGAs for virtual FPGA lab classes.


This Udemy course, "Pipelining RISC-V with Transaction-Level Verilog," led by Steve Hoover and Kunal Ghosh includes numerous hands-on exercises to learn TL-Verilog.

Excellent presentation, examples and impressive tools. Perfect combination to offer so many concepts in just 3hs.

-- Federico Tula Rovaletti, Professor of Computer Eng., Univ. Nacional de Río Negro

This 1-hr video, presented by Steve Hoover introduces TL-Verilog for verification engineers, highlighting the benefits of timing abstraction and transaction-level design for simplifying test harness construction and for making verification collateral more resilient to design changes.

In this anonymous survey after a first lecture on TL-Verilog, one student commented: “I would give my left nut to use this instead of VHDL.”

We can help with the transition. It takes time; we know. Often, we can help with guest lectures and course materials to help get things started. We'll be happy to discuss your needs.



We believe strongly in the importance of collaborations between industry and academia. With Politecnico di Milano’s NECSTLab we pioneered the democratization of cloud FPGAs and the use of cloud FPGAs to accelerate web and cloud applications through the development of 1st CLaaS.

Where you are currently using Verilog/SystemVerilog, it's a no-brainer to speed up your research using TL-Verilog. In addition, TL-Verilog presents many opportunities for breaking new ground in microarchitecture and EDA. Transaction-level design is a new paradigm that is currently in its infancy, so now is the ideal time to impact our future.

Here are just a few research topics of particular interest to us.

  • TL-Verilog component libraries--the Standard Template Library of TL-Verilog

  • Future transaction-level language capabilities

  • Hardware acceleration of web and cloud applications

  • Flexible, adaptable, configurable open-source design IP

  • RISC-V customization/extension using WARP-V

Copyright 2020, Redwood EDA