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Reviewer Comments for: "Accelerating Chip Design with Transaction-Level Verilog"


Reviewer #1:

The paper presents Transaction-Level Verilog (TL-Verilog), a language extension of SystemVerilog. One of it uses is to simplify pipeline design. There are special language elements to express explicitly pipeline stages and pipeline registers. As the result, TL-Verilog code is much simpler than Verilog code for any pipeline design. The paper includes several code examples to demonstrate the simplicity. As a designer, I like TL-Verilog.

Reviewer #2:


This paper presents Transaction-Level Verilog, a hardware description language abstraction that abstracts-away some of the complexities of RTL design without relinquishing control over the physical design to a high-level synthesis tool. The goal is to improve programmability of RTL allowing it to be used in more complex designs instead of relying on modular SoC-like design or high level synthesis which can be less energy efficient.

The paper does a good job at explaining the benefits of TL Verilog over pure RTL or SystemC. I think the language extension provides clear benefits in terms of increasing the expressiveness and power of Verilog. Since most designs today revolve around pipelines, structuring the code around the pipeline construct and having the compiler infer the pipeline registers, timing coordination, etc. has clear benefits.

I especially liked the support for conditionals built into TL Verilog and their application to clock gating. I think this is an interesting contribution.


Reviewer #3:

The author adds language extensions to Verilog, called TL-Verilog, to allow for more native expression of pipelined architecture, where it is claimed that HLS tools can be burdensome for intensive designs.  Because altering a pipeline in RTL requires a nontrivial modification of timing signals, often bugs will arise for a logically simple change.  This is productive solution to a common problem.

Much of the paper is spent explaining the language itself and motivating its elegance.  A small case study at the end shows the language extensions lower code size substantially, which will reduce bugs.