© Copyright 2018 Redwood EDA

Welcome to Redwood EDA!

Redwood EDA's revolutionary technology for integrated circuit design is the culmination of decades of design methodology innovation. It is motivated by experience designing the world's most advanced silicon for high-performance computing.

"Wow, this is freakin' awesome!!!"

         --Michael Cochran, Verification Engineer

"This industry definitely needs to be disrupted."

         --Wojciech Magda, Hardware Engineer

Benefits

 

Our tools enable a net 40% productivity boost for logic designers, as well as benefits for verification, by extending your existing SystemVerilog design environment with support for Transaction-Level Verilog (TL-Verilog).

 

Versus SystemVerilog, TL-Verilog offers:

  • consistently 1/2 the source code to express identical logic!

  • generally 1/4 the code churn for physical design closure and code reuse!

 

TL-Verilog IP is flexible, so it is far easier to retarget to new environments. The WARP-V CPU generator, for example, can be configured as a 1-stage low-frequency microcontroller or as a 7-stage high-frequency CPU!

 
 
Advanced Features

 

As if a 40% productivity boost is not enough, we have Transaction-Level Modeling capabilities that are not yet incorporated into the TL-Verilog standard.  These can be used for early architecture exploration and will completely change the way you design chips and IP blocks.  Your TLMs will come together quickly and can evolve into your final RTL!  Versus SystemVerilog, our TLMs exhibit:

  • about 1/6 the source code!

  • examples of 1/200 the code churn for design changes!

 

TLM features are also appropriate for verification models — fully synthesizable, so you can run your testbench on a hardware emulator and speed simulations ~1000x.

 
 
Incentives

 

Help us gain traction in your organization.  We'll make it easy for you with:

 

Free Starter Tools: SandPiper™ Starter Edition, with complete support for TL-Verilog 1a, will get you going at no cost.  (For broad team use, our Full Edition is more appropriate.)

 

One Free Full Lifetime License: While we build traction, we are offering every company one free lifetime Full License for the latest version of SandPiper.

 

Free Pilot Program (Massachusetts, only): We value a close customer engagement.  For Massachusetts sites (others please inquire), we are offering, for a limited time, a Pilot Program that is absolutely free.  We help boost the productivity of your entire team with on-site consultation.  Participation is further incentivized with access to SandPiper Full Edition and discounted future pricing.

 

 

RTL Model

SystemVerilog

TL-Verilog

SystemVerilog

Transaction-Level Model

TL-Verilog

 

TL-Verilog

 

Better methodology starts with better fundamentals.  Verilog has been the de facto standard design language for over 30 years, and it carries with it a great deal of baggage.

 

TL-Verilog extends SystemVerilog with powerful new language constructs for pipelines and transactions that match the way designers think.  It separates behavior from implementation to provide modeling that spans the spectrum from architect to logic designer to verification engineer and physical designer.  At the same time, it eliminates the need for designers to worry about legacy notions inherent in Verilog, such as generate blocks, blocking vs. non-blocking assignments, packed vs. unpacked datatypes, always blocks, sensitivity lists, reg vs. wire vs. logic vs. bit, etc.

 

TL-Verilog is not another standard driven by corporate money.  It is a grassroots movement to clean house -- a noble mission that Redwood EDA fully embraces.  You can learn more about TL-Verilog at TL-X.org.

 

Here's a quick taste.  Below is a pipelined computation of distance ('c') using the Pythagorean Theorem.

In TL-Verilog, this logic can be expressed as:

The code above is also shown in the lower-left panel below.  From it, SandPiper can generate SystemVerilog (or Verilog) code (shown in the right-hand panels) in a variety of coding styles.  dist.sv (lower-right) contains logic translated line-for-line from dist.tlv.  dist_gen.sv (upper-right) contains:

  • signal declarations

  • staging flip-flops

  • clock gating logic (power savings)
     

These are correct-by-construction, so dist.sv, which is a direct translation of the source code, is the focus of debug.  This means you, in essence, debug the source code, which, in this example, is about 1/6 the size of the SystemVerilog code.

 

The "Code Comparison" chart below shows statistics on the TL-Verilog and SystemVerilog code shown in the other three panels.  Click to explore this in its own window.

 

Accompanying Redwood EDA's tools are several open-source tools supporting the TL-Verilog ecosystem including Emacs and Vim TL-Verilog modes.

Try It!

Try other tutorials and make your own TL-Verilog designs at makerchip.com.