In the classroom
Elevating the silicon industry begins with education. With TL-Verilog and Makerchip we are making digital logic more approachable, more accessible, and hands-on from day one. We collaborate with educators and partners to develop open curricula, including virtual and in-person classes in digital logic, computer architecture, and FPGA labs.
Digital Logic Curricula
All too often, students are taught yesterday’s technology when they should be learning the skills that will enable them to impact the future. 35-year-old RTL languages simply cannot sustain the future of this industry, and teaching RTL positions students on the wrong side of the curve.
But let's put language aside. It is the concepts that students must learn. Utilizing the power and simplicity of TL-Verilog and Makerchip, students learn more in less time.
In the Microprocessor for You in Thirty Hours (MYTH) workshop, offered by VLSI System Design, students with no background in digital logic prove the industry wrong. And we're able to get students at a younger age interested in hardware. Nicholas Sharkey and Niel Josiah are two extreme examples whose blog posts are responsible for about a third of the traffic at the RISC-V International website at the tail end of 2020:
13-year-old, Nicholas Sharkey, Creates a RISC-V Core, RISC-V International Blog
RISC-V Microarchitecture for Kids??!!, RISC-V International Blog
In the first two days of the workshop, students learn about the RISC-V ISA and tools. In the remaining three days, they learn digital logic and build their own pipelined RISC-V CPU cores. Many students have gotten their RISC-V cores on the official list hosted by RISC-V International.
Using TL-Verilog and Makerchip in online training has renewed interest in digital design in India and globally.
VLSI Training Expert and Founder of VLSI System Design
Professors are discovering how much more they can cover using TL-Verilog.
TL-Verilog represents an exciting new direction in HDL’s...
...it removes many of the stumbling blocks that conventional languages put in the way of new students learning to design using HDL’s.
ECE Dept., Brigham Young University
Where does this impact come from?
TL-Verilog simplifies. With VHDL and Verilog, classes get bogged down by the details of the language. TL-Verilog eliminates from Verilog the need for:
blocking vs. non-blocking assignments
packed vs. unpacked datatypes
reg vs. wire vs. logic vs. bit
These are a constant source of confusion for students (and professionals alike) and have nothing to do with digital logic.
Language == concepts. By learning TL-Verilog, students learn a clear thought process for advanced logic design. The constructs of the language are the concepts to be taught:
And the Makerchip online IDE makes it so easy to get started that, in the time it took you to read this far, your students could be coding and simulating their first combinational logic.
In this anonymous survey after a first lecture on TL-Verilog, one student commented: “I would give my left nut to use this instead of VHDL.”
Steve Hoover presents ideas for professors faced with the challenge of converting to remote learning. He demonstrates the value of Makerchip for digital logic classes and the use of cloud FPGAs for virtual FPGA lab classes.
TL-Verilog and Makerchip are ideal for:
Intro to Digital Logic
FPGA Design Labs
Browse our training material for examples of how quickly students can learn.
We can help with the transition. It takes time; we know. Often, we can help with guest lectures and course materials (which evolve continually). We'll be happy to discuss your needs and share what we can.
It is particularly challenging to provide a hands-on lab experience when students are studying remotely.
Our open-source 1st CLaaS cloud FPGA framework is ideal for virtual FPGA labs.
Not only does 1st CLaaS address the need for virtual labs, it also presents an opportunity to teach students emerging technology trends. The availability of FPGAs in the data center opens doors for exciting new computing models that will shape our future. Your students can experience that future first-hand.
Under the umbrella of India's Virtual Labs initiative, we are working to make remote FPGA labs a reality for students across India.
We also have a working relationship with InAccel, who has expertise with FPGA resource-sharing solutions enabling a large class of students to share a limited number of FPGAs.
We believe strongly in the importance of collaborations between industry and academia. For example, we are proud of our work with Politecnico di Milano’s NECSTLab to pioneer the democratization of cloud FPGAs and the use of cloud FPGAs to accelerate web and cloud applications through the development of 1st CLaaS.
So how can we work together? Well, for starters, anywhere you are currently using Verilog/SystemVerilog, it's a no-brainer to speed up your research using TL-Verilog. But let's take a broader view. Transaction-level design is a new paradigm offering a wealth of opportunities for new innovation, so now is the ideal time to make your mark on the industry.
Here are just a few research topics of particular interest to us.
TL-Verilog component libraries--the Standard Template Library of TL-Verilog
Future transaction-level language capabilities
Hardware acceleration of web and cloud applications
Flexible, adaptable, configurable open-source design IP
RISC-V customization/extension using WARP-V
We maintain an active list of opportunities.
How does our technology relate to your research? We'd love to explore that question together.