In the classroom
Elevating the silicon industry begins with education. With TL-Verilog and Makerchip we are making digital logic more approachable, more accessible, and hands-on from day one. We collaborate with educators and partners to develop open curricula, including virtual and in-person classes in digital logic, computer architecture, and FPGA labs. We also offer a summer program.
Steve Hoover presents ideas for professors faced with the challenge of converting to remote learning. He demonstrates the value of Makerchip for digital logic classes and the use of cloud FPGAs for virtual FPGA lab classes.
TL-Verilog and Makerchip are ideal for:
Intro to Digital Logic
FPGA Design Labs
Digital Logic and Computer Architecture Curricula
The EDA industry is finally recognizing that RTL is a legacy design methodology that cannot sustain the industry going forward. Yet universities continue to teach RTL to align with current job openings. This positions students as the low-cost alternative in a flooded market of RTL engineers, and it perpetuates the holding pattern the industry has been stuck in for over 30 years. We should be positioning students as pioneers in growth areas, not as followers.
Regardless of your view on which languages and design methodologies will carry this industry forward (and you know our view on that), it's the logic and microarchitectural concepts that students must learn first. TL-Verilog and Makerchip have been used successfully to teach fundamental concepts in less time.
Students can, in fact, with no experience, build a pipelined CPU from scratch in a week. They do just that in the Microprocessor for You in Thirty Hours (MYTH) Workshop, offered by VLSI System Design. While this course is geared toward college students and professionals, at ages 12 and 13, Niel Josiah and Nicholas Sharkey completed the workshop successfully, creating a bit of a stir in the RISC-V community and proving to the world that digital circuit design can be fun at any age.
13-year-old, Nicholas Sharkey, Creates a RISC-V Core, RISC-V International Blog
RISC-V Microarchitecture for Kids??!!, RISC-V International Blog
Public-domain course content for RISC-V and other TL-Verilog/Makerchip-based courses is available. Every student should learn this way. These folks agree.
Using TL-Verilog and Makerchip in online training has renewed interest in digital design in India and globally.
VLSI Training Expert and Founder of VLSI System Design
TL-Verilog represents an exciting new direction in HDL’s...
...it removes many of the stumbling blocks that conventional languages put in the way of new students learning to design using HDL’s.
ECE Dept., Brigham Young University
Professors at the Technical University of Gabrovo independently structured their digital logic curriculum around TL-Verilog and Makerchip. They published multiple papers about their approach (papers 1 & 2). Here's why they chose TL-Verilog:
TL-Verilog simplifies. With VHDL and Verilog, classes get bogged down by the details of the language. TL-Verilog eliminates from Verilog the need for:
blocking vs. non-blocking assignments
packed vs. unpacked datatypes
reg vs. wire vs. logic vs. bit
These are a constant source of confusion for students (and professionals alike) and have nothing to do with digital logic.
Language == concepts. By learning TL-Verilog, students learn a clear thought process for advanced logic design. The constructs of the language are the concepts to be taught:
In addition to the language benefits, the Makerchip online IDE makes it easy to get started. In the time it took you to read this far, your students could be coding and simulating their first combinational logic. Visual Debug features in Makerchip enhance the learning experience, enabling students to see the operation of their circuits.
RISC-V CPU Visualization in Makerchip for MYTH Workshop
In this anonymous survey after a first lecture on TL-Verilog, one student commented: “I would give my left nut to use this instead of VHDL.”
Makerchip-app enables local TL-Verilog development for any FPGA (or ASIC) tool flow. For FPGA lab classes, Makerchip can be used as a virtual FPGA lab platform to extend the FPGA design experience beyond the physical lab.
Makerchip as a Virtual FPGA Lab
Exported to a Physical FPGA
Even without access to physical FPGAs, we simplify the task of using FPGAs in the cloud using our open-source 1st CLaaS cloud FPGA framework.
Not only does 1st CLaaS address the need for virtual labs, it also presents an opportunity to teach students emerging technology trends. The availability of FPGAs in the data center opens doors for exciting new computing models that will shape our future. Your students can experience that future first-hand.
More Information on Classroom Learning
Browse our training material for examples of how quickly students can learn.
We can help with the transition. It takes time; we know. Often, we can help with guest lectures and course materials (which evolve continually). We'll be happy to discuss your needs and share what we can.
TL-Verilog Summer Program
Offered directly by Redwood EDA, participants learn pre-market Redwood EDA technologies and contribute to open-source projects that are shaping the future of the open-source semiconductor ecosystem and advancing the state of the art. This program is roughly equivalent to two college lab classes with a heavy emphasis on project-based learning.
Currently pursuing a degree in Computer Engineering or a related field with a minimum ~3.2/4.0, ~7.5/10, or equivalent GPA
Introductory experience with TL-Verilog development (which can be gained through these Makerchip-based courses)
Self-discipline and self-motivation
Passion for open-source projects and advancing the semiconductor industry
Excellent remote communication and collaboration skills
Learn advanced circuit design skills, methodologies, and technologies
Work with Redwood EDA CEO, Steve Hoover and other industry leaders and experts in the field
Contribute to the open-source semiconductor ecosystem
Timeline: Minimum 10-week summer commitment, aligned to your college calendar and availability. 6-7 hrs/day with up to 1 week time off.
Cost: $1500 for accepted US participants, due May 15 via PayPal, with geographic discounts for many other countries (e.g. ~40k rupees). Need-based, and merit-based scholarships are available. (Restrictions apply.)
Refunds: The last day for refunds is June 20. The refunded amount is 90% of your enrollment fee. Thereafter, participants who are not putting in the necessary effort will be evicted from the program without a refund. (Restrictions apply.)
To apply, send your resume and cover letter describing reasons for interest to email@example.com. Rolling admission. Decisions within three weeks of application.
We believe strongly in the importance of collaborations between industry and academia. For example, we are proud of our work with Politecnico di Milano’s NECSTLab to pioneer the democratization of cloud FPGAs and the use of cloud FPGAs to accelerate web and cloud applications through the development of 1st CLaaS.
So how can we work together? Well, for starters, anywhere you are currently using Verilog/SystemVerilog, it's a no-brainer to speed up your research using TL-Verilog. But let's take a broader view. Transaction-level design is a new paradigm offering a wealth of opportunities for new innovation, so now is the ideal time to make your mark on the industry.
Here are just a few research topics of particular interest to us.
AI-based circuit design
TL-Verilog component libraries--the Standard Template Library of TL-Verilog
Future transaction-level language capabilities
Hardware acceleration of web and cloud applications
Flexible, adaptable, configurable open-source design IP
RISC-V customization/extension using WARP-V
We maintain an active list of opportunities.
How does our technology relate to your research? We'd love to explore that question together.