TL-Verilog

 

Redwood EDA fully embraces and actively contributes to the emerging Transaction-Level Verilog (TL-Verilog) standard. We believe transaction-level design has the potential to be the most impactful methodological advancement this industry has seen in decades.

Top 10 reasons why we’ve gone all-in on TL-Verilog:

10.

A next-generation ASIC should not take a team of 300 four years to create.

9.

FPGA-based innovation is inhibited by modeling complexity.

8.

Using C++ to design silicon is absurd.

7.

While abstraction is necessary, designers also need gate-level control.

6.

The benefits extend beyond logic design to arch., verif., impl., and post-Si.

5.

TL-Verilog is a zero-overhead enhancement, not a disruptive substitution.

4.

½ the code means ½ the bugs.

3.

TL-Verilog was envisioned with reuse and SoC/IP design in mind.

2.

Engineers and students can learn TL-Verilog in a matter of hours.

1.

Logic design should be fun!

Simple

You'll never again get tripped up by

  • blocking vs. non-blocking assignments

  • packed vs. unpacked datatypes

  • generate blocks

  • always blocks

  • sensitivity lists

  • reg vs. wire vs. logic vs. bit

Powerful

  • Pipelines, transactions, and state are fundamental constructs.

  • High-level models can be composed quickly and RTL details can be filled in over time.

  • TL-Verilog is good for architectural and synthesizable verification models. too.

Flexible

  • Cycle-level details live "below the surface" of the behavioral model. This enables RTL changes to be made without bugs and without impacting verification models.

  • The same IP can be utilized under a wide variety of design constraints.

TL-Verilog Specification

 

TL-X (TL-Verilog, TL-VHDL, TL-C, etc.) language specs are available at tl-x.org. These twelve or so pages will simplify your life like you never thought possible.

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With these TL-Verilog constructs, half of the content in your shelf of Verilog/SystemVerilog books and manuals becomes obsolete.

  • Combinational and Sequential Logic: $signals and expressions

  • Pipelines: |pipelines and @stages

  • Validity: ?$valid

  • Pipeline interactions: >>alignment

  • Hierarchy: /hierarchy

  • State: $State

  • Transaction Flows: $ANY

  • File Structure: \SV, \SV_plus, \TLV, \TLV_version

 

Smaller is better

 

Less code means faster development, fewer bugs, easier maintenance, and better quality silicon. Here are some examples you can find in Makerchip.

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Basic Logic Example
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Cellular Automation: Conway's Game of Life Simulation Circuit

(AKA, this in hardware)

SystemVerilog
TL-Verilog
Transaction-Level Design Example
 
Calculation in a Backpressured Pipeline
SystemVerilog
TL-Verilog
Flexible IP Example
 
WARP-V CPU Core Generator
TL-Verilog
SystemVerilog
Microcontroller

...

...generates these and more.

SystemVerilog
4-stage Core
SystemVerilog
6-stage Core
 

A Quick Taste

 

Below is a pipelined computation of distance ('c') using the Pythagorean Theorem.

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In TL-Verilog, this logic can be expressed as:

The code above is also shown in the lower-left panel below.  From it, SandPiper can generate SystemVerilog (or Verilog) code (shown in the right-hand panels) in a variety of coding styles.  dist.sv (lower-right) contains logic translated line-for-line from dist.tlv.  dist_gen.sv (upper-right) contains:

  • signal declarations

  • staging flip-flops

  • clock gating logic (power savings)
     

These are correct-by-construction, so dist.sv, which is a direct translation of the source code, is the focus of debug.  This means you, in essence, debug the source code, which, in this example, is about 1/6 the size of the SystemVerilog code.

 

The "Code Comparison" chart below shows statistics on the TL-Verilog and SystemVerilog code shown in the other three panels.  Click to explore this in its own window.

 

Try It!

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Try other tutorials and make your own TL-Verilog designs at makerchip.com.

 

Copyright 2020, Redwood EDA