Redwood EDA fully embraces and actively contributes to the emerging Transaction-Level Verilog (TL-Verilog) standard. We believe transaction-level design has the potential to be the most impactful methodological advancement this industry has seen in decades.
Top 10 reasons why we’ve gone all-in on TL-Verilog:
TL-X (TL-Verilog, TL-VHDL, TL-C, etc.) language specs are available at tl-x.org. These twelve or so pages will simplify your life like you never thought possible.
With these TL-Verilog constructs, half of the content in your shelf of Verilog/SystemVerilog books and manuals becomes obsolete.
Combinational and Sequential Logic: $signals and expressions
Pipelines: |pipelines and @stages
Pipeline interactions: >>alignment
Transaction Flows: $ANY
File Structure: \SV, \SV_plus, \TLV, \TLV_version
Smaller is better
Less code means faster development, fewer bugs, easier maintenance, and better quality silicon. Here are some examples you can find in Makerchip.
A Quick Taste
Below is a pipelined computation of distance ('c') using the Pythagorean Theorem.
In TL-Verilog, this logic can be expressed as:
The code above is also shown in the lower-left panel below. From it, SandPiper can generate SystemVerilog (or Verilog) code (shown in the right-hand panels) in a variety of coding styles. dist.sv (lower-right) contains logic translated line-for-line from dist.tlv. dist_gen.sv (upper-right) contains:
clock gating logic (power savings)
These are correct-by-construction, so dist.sv, which is a direct translation of the source code, is the focus of debug. This means you, in essence, debug the source code, which, in this example, is about 1/6 the size of the SystemVerilog code.
The "Code Comparison" chart below shows statistics on the TL-Verilog and SystemVerilog code shown in the other three panels. Click to explore this in its own window.