Papers and Presentations
For this session, Steve Hoover called upon fellow innovators, Jan Kuper and Jose Renau, to showcase to the industry the breadth of opportunity that exists between RTL and high-level synthesis. The session covered the methodologies behind TL-Verilog, Clash, and Pyrope, three modern HDLs that are not simply better RTL languages, they are languages that are better than RTL.
Unleashing the Potential of Open-Source Silicon
Steve Hoover describes the eminent transformation of the silicon industry resulting from cloud FPGAs, which will unlock a vibrant open-source silicon ecosystem, and introduces the 1st CLaaS open-source framework for developing FPGA microservices to accelerate web and cloud application, recognized by Google as a game-changer.
Open Source Silicon Trends and Opportunities
There is great enthusiasm for open-source silicon, but there are obstacles... though not for long!
Top- Down Transaction-Level Design with TL-Verilog
Steve Hoover and Ahmed Salman, VSDOpen, October 2018. (paper)
This paper provides an early look at advanced modeling capabilities for flexible IP reuse. "Top-down design has long been explored, but it is, today, generally understood to be infeasible. We show that it is not."
Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator
This work demonstrates the extreme benefits of timing abstraction and transaction-level design for verification modeling.
ORConf 2018, Akos Hadnagy
VSDOpen 2018, Akos Hadnagy
Timing-Abstract Circuit Design in Transaction-Level Verilog,
Timing-abstract design is a fundamental modeling premise of TL-Verilog. In the anonymous words of the reviewers:
"As a designer, I like TL-Verilog."
"This is a productive solution to a common problem."
"I especially liked the support for conditionals built into TL-Verilog and their application to clock gating."