Papers and Presentations
Timing-abstract design is a fundamental modeling premise of TL-Verilog. In the anonymous words of the reviewers:
"As a designer, I like TL-Verilog."
"This is a productive solution to a common problem."
"I especially liked the support for conditionals built into TL-Verilog and their application to clock gating."
There is great enthusiasm for open-source silicon, but there are obstacles... though not for long!
Top- Down Transaction-Level Design with TL-Verilog, Steve Hoover and Ahmed Salman, VSDOpen, October 2018. (paper)
An early look at advanced modeling capabilities for flexible IP reuse. "Top-down design has long been explored, but it is, today, generally understood to be infeasible. We show that it is not."
This work demonstrates the extreme benefits of timing abstraction and transaction-level design for verification modeling.
ORConf 2018, Akos Hadnagy
VSDOpen 2018, Akos Hadnagy
This talk describes the eminent transformation of the silicon industry resulting from cloud FPGAs, which will unlock a vibrant open-source silicon ecosystem, and introduces the 1st CLaaS open-source framework for developing FPGA microservices to accelerate web and cloud application, recognized by Google as a game-changer.