Training and Publications
Training
With a strong need to educate a global workforce in hardware design skills, global training experts turn to our tools and expertise to get the job done. With the help of VLSI System Design, the Open Source FPGA Foundation, and others, we provide plenty of options for hands-on learning using TL-Verilog and Makerchip.
Our Training Partners:
Our Offerings:
Coming soon, via the Open Source FPGA Foundation, this 1-hour Getting Started with FPGAs primer will get you up and running on various FPGAs boards.
The Building a RISC-V CPU Core course targets the hardware-curious. Offered by Linux Foundation and hosted on EdX, it uses Makerchip and TL-Verilog to teach basic principles of digital logic. In about 10 hours, you can learn digital logic and build a simple RISC-V CPU core.
In this two-hour tutorial session in Silicon Institute of Technology's NES 2020 Conference, Steve Hoover introduces TL-Verilog and Makerchip.
With our training partner, VLSI System Design, we occasionally offer interactive online training, including the 5-day Microprocessor for You in Thirty Hours (MYTH) Workshop, where, with no circuit design experience, you can create your own pipelined RISC-V core.
The video to the left promotes a 2-hour version of the training offered in VSDOpen 2020, which you can now access for free!
This online course, "Pipelining RISC-V with Transaction-Level Verilog," led by Steve Hoover and Kunal Ghosh includes numerous hands-on exercises to learn TL-Verilog.
Excellent presentation, examples and impressive tools. Perfect combination to offer so many concepts in just 3hs.
-- Federico Tula Rovaletti, Professor of Computer Eng., Univ. Nacional de Río Negro
This 1-hr video, presented by Steve Hoover introduces TL-Verilog for verification engineers, highlighting the benefits of timing abstraction and transaction-level design for simplifying test harness construction and for making verification collateral more resilient to design changes.
Papers and Presentations
Transcending RTL
Steve Hoover, Jan Kuper, Jose Renau Invited Session, 57th Design Automation Conference, July 2020.
For this session, Steve Hoover called upon fellow innovators, Jan Kuper and Jose Renau, to showcase to the industry the breadth of opportunity that exists between RTL and high-level synthesis. The session covered the methodologies behind TL-Verilog, Clash, and Pyrope, including an apples-to-apples code comparison. These three modern HDLs are not simply better RTL languages, they are languages that are better than RTL.
Unleashing the Potential of Open-Source Silicon
Steve Hoover, Invited talk, VSDOpen, October 2019. (slides)
Steve Hoover describes the eminent transformation of the silicon industry resulting from cloud FPGAs, which will unlock a vibrant open-source silicon ecosystem, and introduces the 1st CLaaS open-source framework for developing FPGA microservices to accelerate web and cloud application, recognized by Google as a game-changer.
Open Source Silicon Trends and Opportunities
Steve Hoover, Invited talk, VSDOpen, October 2018. (slides)
There is great enthusiasm for open-source silicon, but there are obstacles... though not for long!
Top- Down Transaction-Level Design with TL-Verilog
Steve Hoover and Ahmed Salman, VSDOpen, October 2018. (paper)
This paper provides an early look at advanced modeling capabilities for flexible IP reuse. "Top-down design has long been explored, but it is, today, generally understood to be infeasible. We show that it is not."
Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator
Steve Hoover and Ákos Hadnagy, ORConf and VSDOpen, September and October 2018. (paper, slides)
This work demonstrates the extreme benefits of timing abstraction and transaction-level design for verification modeling.
ORConf 2018, Akos Hadnagy
VSDOpen 2018, Akos Hadnagy
Timing-Abstract Circuit Design in Transaction-Level Verilog,
Steve Hoover, ICCD, November 2017. (paper & slides)
Timing-abstract design is a fundamental modeling premise of TL-Verilog. In the anonymous words of the reviewers:
"As a designer, I like TL-Verilog."
"This is a productive solution to a common problem."
"I especially liked the support for conditionals built into TL-Verilog and their application to clock gating."
Articles
Visual Debug for Formal Verification, by Steve Hoover, posted on SemiWiki and Linkedin, April 2022.
A Free RISC-V CPU Core Builder – Democratizing CPUs, by Steve Hoover, posted on SemiWiki and riscv.org.
Silicon Industry Predictions for 2020, by Steve Hoover. Each year EDACafe publishes industry predictions from influential EDA companies. We predicted major disruption in the coming decade, but no, we did not predict a global pandemic.
Verifying a RISC-V in 1 Page of Code!, by Steve Hoover, Published on LinkedIn and SemiWiki, Nov 2018. Exposes the magic of TL-Verilog for Verification modeling. The more casual counterpart to "Formally Verifying WARP-V."
Outstanding. Every Verification Engineer needs to read this, study it, Grok it. It is a learning experience.
--Mike Wellington, Verification Engineer
Open-Source Hardware Projects That Will Shape the Future, by Steve Hoover, Published on LinkedIn, April 2018. Discusses how the stage is set for the silicon industry to be transformed by an explosive open-source hardware movement in the next decade, and a few active TL-Verilog projects that are helping things along.
A Better Life for RTL Designers, by Steve Hoover, Published on LinkedIn, January 2018. Reveals the opportunities that led Steve to start a new life in a land left for waste.
Transaction-Level Verilog -- The World’s First Hardware Description Language, by Steve Hoover, Published on LinkedIn, September 2017. Explains how TL-Verilog is fundamentally different.
Keep It Simple, Silly! Verilog has how many ways to replicate logic?, by Steve Hoover, Published on LinkedIn, March 2016. Dives into design hierarchy, and how Verilog confuses the matter in ways that probably never occurred to you.