Redwood EDA’s tools accelerate Verilog/SystemVerilog development substantially. They extend your existing Verilog/SystemVerilog development environment with:
visual debug capabilities
integrated design and debug
advanced support for the next, and most impactful, evolution of Verilog -- TL-Verilog
Let's get you upgraded to TL-Verilog, shall we!
The SandPiper™ code generator helps you write Verilog or SystemVerilog code more productively. It is the first and best commercial tool to support TL-Verilog (versions 1a-1d). It generates, from TL-Verilog code, readable, well-structured, Verilog or SystemVerilog code.
SandPiper is freely accessible for open-source development. For commercial use, your organization will pay a fraction of your benefit.
SandPiper™ is accessible in numerous ways:
As a free service (SaaS). Learn more
As a download
Linux and Mac OS X
Windows and Other Platforms
Our initial focus is on Linux customers, but SandPiper can be run on other platforms. Just ask, and we'll hook you up.
When downloading, you can select among the following licenses.
Starter Edition is designed to make you, as a logic designer, more productive within your organization (for free). No special license is required.
Full Edition is built for broad use across a team. Contact us for details.
For educational use.
SandPiper supports the latest TL-Verilog language specification, to make your RTL:
It supports numerous modes to control the automatic generation of Verilog and SystemVerilog to uniformly adhere to your style preferences and to optimize for different use models. In general usage, for development, the output is partitioned between generated code, which is correct-by-construction, and translated code that remains line-for-line with the TL-Verilog source code. This preserves readability and ensures that downstream messages reported against the Verilog/SystemVerilog relate, just as well, to your TL-Verilog source code, so no productivity is lost due to the translation.
The SandPiper download and web/cloud options support the experimental macro-preprocessing capabilities, showcased in the WARP-V CPU core, used to achieve an unprecedented level of IP flexibility.
These popular text editors and integrated development environments (IDEs) support TL-Verilog, with features like syntax highlighting, auto-indentation, compilation, etc.